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ANSYS LUMERICAL
From device analysis and measurement results, it generates compact models usable in circuit simulation. Models for individual elements are collected into a library, which can be shared within a design team or distributed as the model library of a foundry PDK.
Overview
Some device analysis results, S-parameters for instance, can be read straight into INTERCONNECT. But raw data for one set of conditions is not reusable. For a design team to use it repeatedly, analysis and measurement data has to be organized into compact models that circuit simulation can use. Where needed, dimensions, temperature and bias conditions can be parameterized.
CML Compiler performs that conversion systematically. From device analysis and measurement results it generates compact models and collects them into a library.
It is used both when a foundry prepares a PDK and when a company standardizes its own device library internally. It avoids the situation where every designer has a different model.
What CML Compiler gives you
01
Generates models that take dimensions and operating conditions as arguments.
02
Several elements can be collected into a library and distributed as the model library of a PDK.
03
You can confirm that the generated model is consistent with the input data.
Where it fits
For some problems another method solves faster and more accurately. The following is a guide to choosing.
Use CML Compiler to
Consider another method
Turning device analysis or measurement results into compact models and reusing them in circuit simulation.
Typical applications
A device library common to the design team
Inputs and outputs
From the measurement and analysis data you collect, it generates models usable in a circuit simulator.
INPUT
| Analysis results and measured values | Output from FDTD, MODE, CHARGE or HEAT, or measured data |
| Parameter definitions | The dimensions and conditions to take as model arguments |
| Templates | Model templates for each element type |
| Verification conditions | The range of conditions over which the model is confirmed valid |
CML Compiler
Compact model generation
OUTPUT
| CML for INTERCONNECT | The compact model library used in INTERCONNECT |
| Library | A distributable package containing several elements |
| QA test results | Comparison against the source data, regression, and verification of passivity and reciprocity |
| Verilog-A models | Models and symbols for use in an EDA environment |
Analysis workflow
A model can never be more accurate than the data it came from. How complete you can make that source data determines the quality of the library.
01
Collect measured values, or FDTD, MODE, CHARGE or HEAT analysis results, for each element. Automatic data collection workflows are provided for waveguides, S-parameters, electrical phase shifters and thermal phase shifters.
02
Generate the library source directory from a template and choose the model that suits each element.
03
Use the verification command to check the data for gaps and formatting, then generate the CML for INTERCONNECT and the Photonic Verilog-A model from the same source data. Photonic Verilog-A is generated for either Cadence Virtuoso or Synopsys OptoCompiler. Please see the latest system requirements for the releases supported.
04
Depending on the photonic model, agreement with the input data, regression, passivity and reciprocity, and consistency between frequency and time domain are all verified automatically.
05
Version and distribute the library. In INTERCONNECT an encrypted CML is installed from Design Kits; in an EDA environment the library definition and include files are loaded.
Frequently asked questions
Questions we are often asked before adoption.
Which elements are supported?
Templates are provided per element type, from passive elements through to active ones. Custom models can also be defined.
How do I confirm a generated model is valid?
A QA testbench is generated for each element, letting you compare the response of the input data and the generated model within a tolerance you set. Depending on the photonic model, regression, passivity and reciprocity checks are also run. The reference for accuracy is the source data you supplied, so accuracy under conditions that data does not cover cannot be confirmed.
Is it used outside foundries?
Yes. Where several designers in one organization work on the same element, keeping the model consistent is what makes comparing results meaningful.
Can it be used alongside an existing PDK?
Yes, though you need to confirm compatibility between the simulation environment you are using and the model format. In INTERCONNECT an existing CML and a CML you generated yourself can be used in the same circuit. If you use Photonic Verilog-A alongside an existing foundry PDK, check that the PDK’s model format and port conventions are supported. Note that an INTERCONNECT compact model and a Photonic Verilog-A model cannot be connected optically within the same circuit.
We can advise on everything from simulation setup to judging whether a result is sound. Hands-on training is also available.
Support →
Training →
You do not need to share everything. Whatever you are able to tell us is enough.
The demo uses subject matter close to your own. We can also give you an idea of the configuration required and the time it takes.