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ANSYS LUMERICAL
Individual device characteristics are connected as compact models to evaluate the performance of a photonic circuit and of the link as a whole. You can see straight away how a change to a device design affects system performance.
Overview
A device that performs well on its own will not necessarily meet specification once it is built into a circuit. Accumulated insertion loss, multiple interference from reflections, variation between elements — these only become visible when the system is solved as a whole.
S-parameters obtained from FDTD or MODE are imported as compact models and connected in schematic form. Both time-domain and frequency-domain analysis are supported.
Simultaneous electro-optical analysis is also supported, so a transmit and receive system can be evaluated including basic electrical circuit elements. To solve as far as transistor-level drivers and TIAs, EDA integration such as co-simulation with Cadence Spectre is used.
The advantages of INTERCONNECT
01
Data from device analysis or from measurement can be carried into the circuit analysis as compact models.
02
Both eye diagrams and frequency response are covered.
03
Where a statistical model exists, Monte Carlo analysis gives you yield; where process corners are defined, corner analysis gives you the range of performance.
Where it fits
There are cases another method will solve faster and more accurately. The following is a guide to choosing.
Use INTERCONNECT
Consider another method
How single-device analysis and integrated circuit-level analysis divide the work.
Typical applications
Eye opening and BER for the transmit and receive link
Channel allocation and crosstalk
Inputs and outputs
For the circuit configuration and signal conditions you set, transmission characteristics and signal quality are returned.
INPUT
| Compact models | S-parameters, CML libraries, built-in element models |
| Circuit configuration | How the elements are connected |
| Signal source | Modulation format, bit rate, source characteristics |
| Analysis settings | Time domain or frequency domain |
INTERCONNECT
Circuit simulation
OUTPUT
| Eye diagram | Opening, jitter, extinction ratio |
| BER | Bit error rate, Q factor, eye opening ratio |
| Frequency response | Transfer function, group delay |
| Spectrum | Signal power, noise power and OSNR for each channel |
Analysis workflow
Too low a sample rate cannot represent the bandwidth of the time waveform; too short a time window cannot resolve narrow spectral features. Settings chosen to match the purpose of the analysis translate directly into the accuracy of the result.
01
Install the .cml received from the foundry into Design Kits.
02
Place elements from the Element Library or a Design Kit to assemble the circuit. Where needed, import S-parameters or data from measurement or device analysis, in the format the element model expects.
03
Choose between TSM (suited to closed loops), TBM (suited to open loops) and SPS (frequency domain). Sample rate and time window are time-domain settings, for TSM and TBM.
04
Use the Optical Network Analyzer for transmission, group delay and dispersion, and the Eye Diagram for BER and jitter.
05
Beyond parameter sweeps and optimisation, where a statistical model is available Monte Carlo analysis gives you the yield against manufacturing variation. Where the CML defines process corners, corner analysis shows the range of performance for each condition.
EDA integration
Photonic Verilog-A is part of the INTERCONNECT and CML Compiler workflow. Models for an electronic design automation (EDA) environment are generated from the same source data, so a photonic circuit can be handled in the same schematic as the electronic circuit.
INTERCONNECT is for analysing photonic circuits; Photonic Verilog-A is for co-simulation of electronic and photonic circuits inside an EDA environment. Both can draw on the same model source data.
CML Compiler generates the Photonic Verilog-A models, building a library from the source data for each element and distributing it for the EDA environment.
The classic workflow. Load the generated models and symbols into Virtuoso, and take the electronic and photonic circuits through design, simulation and layout in the same schematic.
Supports co-simulation of electronic and photonic circuits using OptoCompiler with PrimeSim SPICE / PrimeSim HSPICE. For supported versions and operating environments, please see the latest system requirements.
There is no license specific to Photonic Verilog-A. On the Ansys side it is available under an INTERCONNECT or Enterprise license, and generating the models requires a CML Compiler license. A license for the EDA tool itself is required separately.
INTERCONNECT compact models and Photonic Verilog-A models pass signals and information in fundamentally different ways, so they cannot be connected optically within the same circuit.
Frequently asked questions
The questions we are most often asked before adoption.
How are FDTD results brought in?
S-parameters extracted in FDTD can be imported as an S-parameter element or a compact model in INTERCONNECT. The modes, ports and frequency or wavelength range must be kept consistent between the two.
Can it be solved together with an electrical circuit?
Yes. INTERCONNECT on its own can analyse electro-optical circuits that include basic electrical circuit elements. For detailed simultaneous analysis of electronic and photonic circuits including transistor-level drivers and TIAs, EDA integration such as co-simulation with Cadence Spectre is used.
Can PDK models be used?
Yes, for any PDK that ships a CML (Compact Model Library) supporting INTERCONNECT. What the CML contains and which versions it supports differ from foundry to foundry and platform to platform, so please check in advance.
Can I add my own element models?
Yes. Custom elements can be defined as a Scripted Element using S-parameters or analytic expressions, or as a Compound Element grouping several elements together.
We can advise on everything from analysis setup to judging whether a result is sound. Hands-on training, where you work with the software yourself, is also available.
Support →
Training →
It is fine if there is information you cannot share — tell us only what you are comfortable with.
The demo is built around material close to your own case. We can also give you an indication of the configuration you would need and the time it takes, on the spot.