Solutions | Photonics
Whether the eye closes at the receiver is the accumulated result of modulator nonlinearity, electrode velocity matching, inter-channel crosstalk, assembly parasitics and receiver noise. Component physics has to be carried through to link metrics, and shown to keep the eye open under variation.
Design challenges
What happens when you change one modulator has to be answered in eye opening, extinction ratio and BER, not in a graph of device characteristics. That causal chain runs across electrical, optical, thermal and assembly behavior, and refining any one of them alone does not produce the answer. Keeping component to circuit, and circuit to statistical analysis, as one continuous chain is what a design environment in this field has to provide.
Design and simulation workflow
Settle the modulation format and channel count, and isolate the dominant sources of degradation.
Obtain the change in index and loss with bias, and the high-frequency characteristics of the electrode.
Model couplers, ring filters and arrayed waveguide gratings.
Obtain the generation rate from optical absorption, and compute responsivity, dark current and bandwidth.
Assemble the whole transmit and receive path and evaluate the eye, BER, extinction ratio and jitter.
Re-verify with corner analysis, Monte Carlo and assembly parasitics included.
The stages differ by project. Only part of an existing transceiver design can be addressed if that is what you need.
Related analysis technologies
The principles and scope of each method are explained on the Analysis Technologies pages.
Related products
The capabilities and coverage of each product are described on its own product page.
Handles design of passive and multiplexing components. FDE and varFDTD solve couplers and arrayed waveguide gratings.
Stage / 03
Handles rigorous analysis of grating couplers and photodetectors. Three-dimensional FDTD gives coupling efficiency and absorption distribution.
Stage / 03-04
Handles the electrical characteristics of modulators and photodetectors. CHARGE gives index change, responsivity and bandwidth, with HEAT alongside it where needed.
Stage / 02, 04
Handles link evaluation and yield verification. The whole transmit and receive path is assembled, covering eye opening, BER, extinction ratio, jitter and corner analysis.
Stage / 05-06
Handles compact model generation. Extracted component characteristics are organized into a model library usable in link analysis.
Stage / 02-04
Foundry and manufacturing
Once the transmitter and receiver chip layout is settled, you move to prototyping through a multi-project wafer (MPW) or a dedicated run. Which constraints apply depends on the target platform and the assembly route, so confirm them alongside the conditions for handing over the design data.
Whether prototyping and manufacturing are possible, and in what form, is judged case by case from the target platform and process conditions.
Related technical information
Tell us where the design stands, the modulation format and channel count, whether models already exist, and how far assembly has progressed, and we will propose a way forward.