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The design workflow for photonic integrated circuits (PICs)

A PIC integrates tens to thousands of components on a single chip. Components are solved rigorously, the circuit with equivalent models. How you build that hierarchy, and where you can join it without losing accuracy, is what the design turns on.

Design challenges

Splitting an unsolvable scale into levels

From the tens of micrometers of a grating coupler to the centimeters of a circuit. No single electromagnetic analysis covers that range. Solve the components rigorously, compress them into compact models, then reassemble as a circuit. Accuracy is quietly lost at every compression, so you need a structure that lets you trace which data each model rests on.

Requirement | model traceabilityEvery compact model traces back to rigorous analysis or measurement, and can be regenerated when the process is updated
Requirement | tolerance to variationCircuit performance can be predicted as a distribution under spatially correlated manufacturing variation
Requirement | working with the electronicsThe photonic circuit can be verified on the same schematic and testbench as the driver circuit

Design and simulation workflow

From component to circuit, and on to yield

01

Rigorous component analysis

Solve the electromagnetic response of each component. For active components, solve carriers and heat as well.

02

Parameter extraction

Reduce to the S-parameters and effective indices the circuit model needs.

03

Compact model construction

Organize them into a versioned, verified model library.

04

Circuit simulation

Build the schematic and evaluate frequency and transient response.

05

Layout and back-annotation

Drive the layout from the schematic, then re-verify against real coordinates.

06

Yield and co-verification

Obtain yield by corner analysis and Monte Carlo, and co-verify with the electronics.

The stages differ by project. You can bring an existing PDK or model assets and start partway through.

Related products

Products used at each step

The capabilities and coverage of each product are described on its own product page.

Lumerical FDTD

Handles rigorous analysis of passive components. Three-dimensional FDTD gives the electromagnetic response of each component.

Stage / 01-02

Lumerical MODE

Handles waveguide and mode analysis and planar propagation. FDE, EME and varFDTD are used according to the structure.

Stage / 01-02

Lumerical Multiphysics

Handles active component and thermal analysis. CHARGE and HEAT give carrier transport and temperature distribution.

Stage / 01-02

Lumerical CML Compiler

Handles compact model generation. Extracted parameters are organized into a versioned model library.

Stage / 03

Lumerical INTERCONNECT

Handles circuit analysis and yield evaluation. Covers frequency and transient response, corner analysis and Monte Carlo.

Stage / 04-06

Foundry and manufacturing

Connecting design data to manufacturing

Once the circuit layout is settled, you move to prototyping through a multi-project wafer (MPW) or a dedicated run. Before handover, confirm that the design follows the process design kit of the target platform and that the layout you output matches the constraints of the manufacturing route you have chosen.

Whether prototyping and manufacturing are possible, and in what form, is judged case by case from the target platform and process conditions.

Talk to us about your target platform and circuit scale

Tell us where the design stands, whether you have a PDK, what model assets already exist, and what you need to verify, and we will propose a way forward.